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IET Computers and Digital Techniques

來源: 樹人論文網 瀏覽次數:209次
周期:Bimonthly
ISSN:1751-8601
影響因子:0.857
是否開源:No
年文章量:27
錄用比:容易
學科方向:計算機:硬件
研究方向:工程技術
通訊地址:INST ENGINEERING TECHNOLOGY-IET, MICHAEL FARADAY HOUSE SIX HILLS WAY STEVENAGE, HERTFORD, ENGLAND, SG1 2AY
官網地址:http://www.ietdl.org/IET-CDT
投稿地址:http://mc.manuscriptcentral.com/iet-cdt
網友分享經驗:>12周,或約稿

IET Computers and Digital Techniques雜志中文介紹

IET計算機和數字技術出版技術論文,描述了電子和嵌入式系統芯片上數字系統設計和測試各個方面的最新研究和開發工作,包括設計自動化工具(方法、算法和體系結構)的開發。基于縮小CMOS技術相關問題的論文尤其受歡迎。它面向計算機和數字系統設計和測試領域的研究人員、工程師和教育工作者。重點關注的主題領域有:設計方法和工具:CAD/EDA工具、硬件描述語言、高級和體系結構綜合、硬件/軟件協同設計、基于平臺的設計、3D堆疊和電路設計、系統芯片架構和IP核心、嵌入式系統、邏輯綜合、低功耗設計和功率優化。仿真、測試和驗證:電氣和定時仿真、基于仿真的驗證、硬件/軟件協同仿真和驗證、混合域技術建模和仿真、硅后驗證、功率分析和估計、互連建模和信號完整性分析、硬件信任和安全、可測試性設計、嵌入式核心測試、系統芯片測試、在線測試、自動測試生成和延遲測試、低功率測試、可靠性、故障建模和容錯。處理器和系統架構:許多核心系統、通用和特定于應用程序的處理器、DSP應用程序的計算算法、算術和邏輯單元、緩存存儲器、內存管理、協處理器和加速器、芯片上的系統和網絡、嵌入式核心、平臺、多處理器、分布式系統、通信協議和低功耗問題。可配置計算:嵌入式核心、FPGA、快速原型、自適應計算、可演化和靜態、動態可重構和可重編程系統、可重構硬件。變率、功率和老化設計:變率、功率和老化感知設計、存儲器、FPGA、IP組件、3D疊加、能量采集的設計方法。案例研究:新興應用、工業設計應用和設計框架。

IET Computers and Digital Techniques雜志英文介紹

IET Computers and Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.The key subject areas of interest are:Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.Case Studies: emerging applications, applications in industrial designs, and design frameworks.

IET Computers and Digital Techniques影響因子

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